n South African Computer Journal - Hardware genetic algorithm optimisation by critical path analysis using a custom VLSI architecture




This paper investigates optimisation of Evolutionary Hardware Systems (EHW) by means of digital circuit critical path analysis. A 2x2 digital multiplier and a Finite State Machine (FSM) control circuit were evolved using a target-independent Virtual Reconfigurable Circuit (VRC) architecture. An in-depth analysis of the phenotypes' Critical Paths (CP) was performed. Through analysing the CPs, it was shown that a great amount of insight can be gained into a phenotype's fitness. Particularly, the identification of the CP's dependence is valuable, since dependent CPs reduced the required net number of evolved Logic Elements (LE). Generally, in both the multiplier and state phenotypes, the CPs were evolved in ascending order of the net LEs. This suggests that evolution always favoured CPs with lower net numbers. However, we have seen that in one special case, if two independent CPs are used by a third CP, the resulting third CP has a lower net number than both independent CPs. The CP analysis also led to the development of the fitness function, which had a distinctive way of not only rewarding correct output elements, but also encouraging more efficient evolution through sustaining evolved CPs, and further developing partially-evolved CPs. Finally, by using the optimized fitness function, we demonstrated the evolution of a FSM control circuit. The results verify that optimised GAs can find solutions quicker, and with fewer attempts.


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